1. Field of the Invention
The present invention provides an electrostatic discharge (ESD) protection device and related circuit. In particular, an ESD protection device with a high substrate-triggered effect is disclosed.
2. Description of the Prior Art
With the continued miniaturization of integrated circuit (IC) devices, the current trend is to produce integrated circuits having shallower junction depths, thinner gate oxides, lightly-doped drain (LDD) structures, shallow trench isolation (STI) structures, and self-aligned silicide (salicide) processes, all of which are used in advanced sub-quarter-micron CMOS technologies. All of these processes cause the related CMOS IC products to become more susceptible to electrostatic discharge (ESD) damage. Therefore, ESD protection circuits are built onto the chip to protect the devices and circuits of the IC against ESD damage. It is generally desired that the ESD robustness for commercial IC products be higher than 2 kV in human-body-model (HBM) ESD stress. To sustain ESD overstress, devices with large dimensions need to be designed into the on-chip ESD protection circuit, and require a large total layout area on the silicon substrate.
Typically, an NMOS in an I/O ESD protection circuit has a total channel width that is greater than 300 xcexcm. With such large device dimensions, the NMOS is often realized with multiple fingers in the layout. However, under an ESD stress, the multiple fingers of ESD protection NMOS do not uniformly turn on to bypass the ESD current. Only a portion of the fingers of the NMOS may be turned on, and consequently leading to damage from the ESD pulse. In this case, although the ESD protection NMOS has a very large device dimension, the ESD protection level is low.
In order to improve the turn-on uniformity among the multiple fingers, a gate-driven design has been used to increase the ESD protection level of the large-device-dimension ESD protection NMOS. However, it has been found that the ESD protection level of the gate-driven NMOS decreases dramatically when the gate voltage is somewhat increased. The gate-driven design pulls ESD current flowing through the channel surface of the NMOS rather than the bulk. The NMOS is thus more easily burnt-out by the ESD energy.
Please refer to FIG. 1. FIG. 1 is a schematic circuit diagram of a traditional ESD protection design using the gate-driven technique. Since all ESD protection designs using the gate-driven technique have the same basic idea, they may be generally illustrated as disclosed in FIG. 1. As shown in FIG. 1, the ESD protection circuit design 10 comprises an ESD protection NMOS 12. The NMOS 12 comprises a source 13, a drain 14 and a gate 16. The drain 14 of the NMOS 12 is electrically connected to a pad 18. The gate 16 is biased by a gate-biasing circuit 20. The gate-biasing circuit 20 is typically designed with a coupled capacitor (not shown) electrically connected from the pad 18 to the gate, and a resistor(not shown) electrically connected from the gate 16 to a VSS power terminal. Additionally, an internal circuit 22 is electrically connected to the pad 18 through a conductor 23.
When a positive ESD voltage zaps the pad 18, a sharp-rising ESD voltage pulse is coupled to the gate 16 of the ESD protection NMOS 12. The ESD protection NMOS 12 is thus turned on to discharge the ESD current from the pad 18 to the VSS power terminal. This is the so-called gate-coupled design or gate-driven design. The gate bias improves the turn-on uniformity of the multiple fingers of the ESD protection NMOS, but an excessive gate bias also causes the ESD current to flow through the inversion layer of the surface channel of the ESD protection NMOS 12, which can burn out the channel of the NMOS 12.
Please refer to FIG. 2. FIG. 2 is a schematic diagram of an ESD current path flowing through a gate-driven NMOS device. As shown in FIG. 2, an ESD protection NMOS device 30 comprises a P substrate 31, a P-well 32 in the P substrate 31, and an NMOS transistor 34 in the P-well 32. The NMOS transistor 34 comprises a source 35, a drain 36 and a doped polysilicon gate 37. Two lightly doped drains (LDD) 38 are adjacent to the source 35 and drain 36, respectively. The source 35 region is electrically connected to a VSS power terminal, the drain 36 region is electrically connected to a pad 40, and the gate 37 region is electrically connected to a gate-biasing circuit 42. In FIG. 2, ESD damage is often located at the surface channel close to the LDD 38 edge of the drain 36.
The gate-biasing circuit 42 generates a high voltage (VG) to bias the gate 37 of the NMOS transistor 34 during positive ESD zapping events. The generated VG gate voltage turns on the surface channel of the NMOS. A surface channel of the NMOS 34 having a structure with a much shallower junction depth and smaller volume is more susceptible to ESD damage. Not only may burn-out occur because of overheating, but the NMOS 34 may also be damaged by ESD. The ESD damage is often located at the surface channel close to the LDD 38 corner of the drain 36. A large ESD current (typically 1.33 Amp, for a 2 kV HMB ESD event), flowing through the very shallow surface channel of the NMOS transistor 34, often burns out the NMOS transistor 34 even if the NMOS 34 has large device dimensions.
Please refer to FIG. 3. FIG. 3 illustrates experimental results of the dependence between gate-biasing voltage and HBM ESD protection level of the NMOS 12 device in a 0.35 xcexcm silicide CMOS process. As shown in FIG. 3, the HBM ESD protection level of the NMOS 12 is initially increased when the gate-biasing voltage increases. But the HBM ESD protection level of the NMOS design decreases sharply when the gate-biasing voltage exceeds a critical voltage level. The ESD protection NMOS 12 in FIG. 3 has a fixed channel length of 0.8 xcexcm. The HBM ESD level of the ESD protection NMOS 12, with W=600 xcexcm, begins to sharply decrease when the gate-biasing voltage is increased beyond about 8.5V. Because of this, the gate-driven design is no longer suitable for use to improve ESD robustness in sub-quarter-micron CMOS technologies.
Please refer to FIG. 4. FIG. 4 is a schematic circuit diagram of another prior art ESD protection design 50 using a substrate-triggered technique. As shown in FIG. 4, the ESD protection circuit design 50 comprises an NMOS 52, an internal circuit 62, a pad 58, a substrate-biasing circuit 60, and a conductor for electrically connecting the internal circuit 62 with the pad 58. The NMOS 52 further comprises a source 53, a drain 54 electrically connected to the pad 58, a gate 55, and a substrate 56 biased by the substrate-biasing circuit 60.
When a positive ESD voltage zaps the pad 58, the bulk (substrate) of the ESD protection NMOS 52 is biased at some voltage level generated by the substrate-biasing circuit 60. With the substrate-biasing voltage, parasitic lateral n-p-n bipolar junction transistor (BJT) 64 effects in the NMOS 52 are triggered on to discharge the ESD current. In this substrate-triggered technique, the ESD current flowing through the NMOS 52 is far from the channel surface. The NMOS 52 can therefore sustain higher ESD levels than those of the gate-driven technique.
Please refer to FIG. 5. FIG. 5 illustrates experimental results of the dependence between the substrate-biasing voltage and the HBM ESD protection level of the ESD protection NMOS 52 device for a 3.35 xcexcm silicide CMOS process. As shown in FIG. 5, the HBM ESD level of the substrate-triggered NMOS 52 always increases when the substrate-biasing voltage increases. This result is significantly different from that of the gate-driven design. The substrate-triggered effect turns on a parasitic lateral n-p-n BJT 64 of the NMOS 52 structure to pull the current to flow through the bulk of the NMOS 52, which is far from the surface channel of the NMOS, and so avoids the drain LDD edge structure. The bulk of the NMOS 52 has a larger volume to dissipate ESD-generated heat. The substrate-triggered NMOS 52 can thus sustain a much higher ESD level within the same silicon area. The substrate-triggered technique has consequently become more important in sub-quarter-micron CMOS processes for effective on-chip substrate-triggered ESD protection.
Please refer to FIG. 6. FIG. 6 is a cross-sectional schematic diagram of an ESD protection NMOS device 70 according to the substrate-triggered design. The ESD protection NMOS device 70 comprises a P substrate 71, a P-well 72 in the P substrate 71, and two NMOS devices 73 in the P-well 72. Each NMOS 73 further comprises a source 75, a drain 76, and a doped polysilicon gate 74. A lightly doped drain (LDD) 79 is adjacent to each source 75 and each drain 76. Two shallow trench isolation (STI) structures 77, 78 are used to isolate each NMOS 73 from other electrical devices. One P+ diffusion region 81 next to the STI 77 is electrically connected to the VSS power terminal, and another P+ diffusion region 80 next to the STI 78 is electrically connected to a substrate-biasing circuit 82. One parasitic lateral n-p-n BJT 84 underneath the NMOS 73 is triggered on by the trigger current (Itrig) conducting from the P+ diffusion region 80 next to the STI 78 when biased by the substrate-biasing circuit 82.
In a typical 0.18 xcexcm CMOS process, the STI structures 77, 78 have a depth of 0.4xcx9c0.5 xcexcm (from the silicon surface), but the source 75, drain 76 diffusion regions have a junction depth of only 0.15 xcexcm. The STI 77, 78 regions with a deeper depth provide better isolation between two adjacent diffusion regions. However, such a deep STI 78 region also degrades the substrate-triggered effect of the ESD protection NMOS 73 device, as the trigger current conducting from the P+ diffusion 80 finds it hard to bias the base of the parasitic lateral n-p-n BJT 84. This results in a slow turning-on of the parasitic lateral n-p-n BJT 84 in the NMOS 73. With a slow turn-on speed of the BJT 84, the NMOS 73 serving as the ESD protection device has a decreased ability to protect the internal circuit (not shown).
It is thus important to develop an ESD protection NMOS to avoid the above-mentioned issues of current flowing through the surface channel, and to avoid the STI slowing down the parasitic lateral n-p-n BJT action of the NMOS device.
It is a primary objective of the present invention to provide an ESD protection device with a high substrate-triggered effect and related circuit so as to increase the turn-on speed of the ESD protection circuit and resolve heat dissipation problems.
In the preferred embodiment of the present invention, the ESD protection device is formed on a P-type well. The ESD protection device comprises a first NMOS and a second NMOS. Three P+ diffusion regions are in the P-type well. The first and the third P+ diffusion regions are used for electrically connecting to a VSS power terminal. The second P+ diffusion region is between the first and the second NMOS to electrically connected to a P-well biasing circuit and therefore to induce a substrate-trigger current (Itrig). A first dummy gate is between the first NMOS and the second P+ diffusion region, a second dummy gate is between the second P+ diffusion region and the second NMOS. A first shallow trench isolation (STI) structure is used to isolate the first NMOS and the first P+ diffusion region, and at least one second STI structure is used to isolate the second NMOS and the third P+ diffusion region. The drain of each NMOS, the source of each NMOS, and the P-type well form a parasitic lateral n-p-n bipolar junction transistor (BJT), respectively. The substrate trigger current (Itrig) flows into the P-type well underneath each dummy gate to turn on each adjacent parasitic lateral n-p-n BJT so the ESD protection device quickly discharges an ESD current to the VSS power terminal.
It is an advantage of the present invention that an additional dummy gate is used to block the shallow trench isolation between the MOS drain diffusion region and the diffusion region connected to the substrate-biasing circuit. Discharging of the ESD current is thus performed more quickly by utilizing the substrate-trigger current Itrig generated from the substrate-biasing circuit. Heat dissipation problems resulting from the ESD current flowing through the surface channel are thus solved. By applying the MOS device structure in the ESD protection circuit according to the present invention, not only is the ESD robustness effectively increased with an overall increase of ESD protection, but also the MOS device structure is fully compatible with standard CMOS processes.